Design and Simulation of a Low Power Viterbi Decoder using Constraint Length Nine

Viterbi Decoder is the dominant module to determining the power consumption of the system. High speed and low power design of Viterbi Decoder with data rate1/2 and convolution encoding with a constraint length K = 9 is presented in this paper. The Proposed Viterbi decoder can be reduce the power consumption without reducing the decoding speed and also increases the length of the bits. The operating frequency of convolution encoder and Viterbi decoded is 306.65MHz and power consumption is 45.01Mw using Xpower tools in Xilinx and Spartan 3E FPGA kit.